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AP393
Low Power Low Offset Voltage Dual Comparators Features
- Wide supply Voltage range: 2.0V to 36V Single or dual supplies: 1.0V to 18V - Very low supply current drain (0.4 mA) - independent of supply voltage - Low input biasing current: 25 nA - Low input offset current: 5 nA - Maximum offset voltage: 3 mV - Input common-mode voltage range includes ground - Differential input voltage range equal to the power supply voltage - Low output saturation voltage: 250 mV at 4 mA - Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic systems - 8-pin PDIP and SOP Pb-Free packages
General Description
The AP393 consists of two independent precision voltage comparators with an offset voltage specification as low as 2.0 mV max for two comparators which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The AP393 is designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, the AP393 will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators.
Advantages
- High precision comparators - Reduced VOS drift over temperature - Eliminates need for dual supplies - Allows sensing near ground - Compatible with all forms of logic - Power drain suitable for battery operation
Pin Assignment
(Top View) OUTPUT 1 1 INVERTING INPUT 1 2 NON-INVERTING INPUT 1 3 GND 4 8 AP393 7 6 5 V+ OUTPUT 2 INVERTING INPUT 2 NON-INVERTING INPUT 2
SOP-8L/PDIP-8L
Pin Descriptions
Pin Name
OUTPUT 1 INVERTING INPUT 1 NON-INVERT ING INPUT 1 GND
Pin No.
1 2 3 4
Description
Channel 1 Output Channel 1 Negative Input Channel 1 Positive Input Ground
Pin Name
NON-INVERT ING INPUT 2 INVERTING INPUT 2 OUTPUT 2 + V
Pin No.
5 6 7 8
Description
Channel 2 Positive Input Channel 2 Negative Input Channel 2 Output Vcc
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Sep 7, 2004 1/13
AP393
Low Power Low Offset Voltage Dual Comparators Ordering Information
AP393 X X
Package N: PDIP-8L S: SOP-8L
Packing Blank: Tube A : Taping
Block Diagram
OUTPUT 1 1 8 V+
INVERTING INPUT 1
2 A B ++ -
7
OUTPUT 2
NON-INVERTING INPUT 1 3
-
6
INVERTING INPUT 2
GND
4
5
NON-INVERTING INPUT 2
V+
3.5A
100A
3.5A
100A
Q2 +INPUT Q1
Q3 Q4 Q5 OUTPUT
-INPUT Q6 Q8 Q7
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Sep 7, 2004 2/13
AP393
Low Power Low Offset Voltage Dual Comparators Absolute Maximum Ratings (Note 10)
Symbol VCC VIN VIN ICC PD TOP TST TLead Parameter Supply Voltage Differential Input Voltage (Note 8) Input Voltage Input Current (VIN-0.3V) (Note 3) Molded DIP Power Dissipation (Note 1) Metal Can Small Outline Package Output Short-Circuit to Ground (Note 2) Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 10 sec) PDIP Soldering (10 sec) Soldering Information Vapor Phase (60 sec) SOP Infrared (15 sec) ESD rating (1.5k in with 100pF) Rating 36 36 -0.3 to +36 50 780 660 510 Continuous 0 to +70 -65 to +150 +260 +260 +215 +220 1300 Unit V V V mA mW
o o
C C o C
o
C
V
Electrical Characteristics (VCC=5V, TA=25oC, unless otherwise stated)
Symbol Parameter VOFFSET Input Offset Voltage IBIAS IOFFSET ICC Input Bias Current Conditions
(Note 9)
Min. 0 50 6.0 -
Typ. 1.0 25 5.0 0.4 1 200 300 1.3 16 250 0.1
Max. 5.0 250 50 V+ -1.5 1 2.5 400 -
Unit mV nA nA V mA V/mV ns s mA mV nA
IO(Sink) VSAT IO(Leak)
IIN(+) or IIN(-) with Output In Linear Range, VCM=0V (Note 5) Input Offset Current IIN(+) - IIN(-) VCM=0V Input Common Mode Voltage Range V+ =30V (Note 6) V+ =5V Supply Current RL= V+ =36V + RL > 15k, V =15V Voltage Gain VO=1V to 11V VIN=TTL Logic Swing, Large Signal Response Time VREF=1.4V, VRL=5V, RL=5.1k Response Time VRL=5V, RL=5.1k (Note 7) Output Sink Current VIN(-)=1V, VIN(+)=0, VO <1.5V VIN(-)=1V, VIN(+)=0, ISINK < Saturation Voltage 4mA Output Leakage Current VIN(-)=0, VIN(+)=1V, VO=5V
Electrical Characteristics (VCC=5V) (Note 4)
Symbol Parameter VOFFSET Input Offset Voltage IOFFSET Input Offset Current IBIAS VSAT IO(Leak) Conditions
(Note 9)
IIN(+) -IIN(-), VCM=0V IIN(+) or IIN(-) with Output In Input Bias Current Linear Range, VCM=0V (Note 5) Input Common Mode Voltage Range V+ =30V (Note 6) VIN(-)=1V, VIN(+)=0, ISINK < Saturation Voltage 4mA Output Leakage Current VIN(-)=0, VIN(+)=1V, VO=30V Keep All VIN's > 0V (or V-, if Differential Input Voltage Used), (Note 8)
Min. 0 -
Typ. -
Max. 9 150 400 V -2.0 700 1.0 36
+
Unit mV nA nA V mV A V
Anachip Corp. www.anachip.com.tw 3/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators
Note 1: For operating at high temperatures, the AP393 must be derated based on a 125C maximum junction temperature and a thermal resistance of 170C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The AP393 must be derated based on a 150C maximum junction temperature. The low bias dissipation and the "ON-OFF" characteristic of the outputs keeps the chip dissipation very small (PD <100 mW), provided the output transistors are allowed to saturate. + Note 2: Short circuits from the output to V can cause excessive heating and eventual destruction. When considering short circuits to + ground, the maximum output current is approximately 20 mA independent of the magnitude of V . Note 3: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output + voltages of the comparators to go to the V voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a value greater than -0.3V. Note 4: The AP393 temperature specifications are limited to 0C < TA < +70C. Note 5: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so no loading change exists on the reference or input lines. Note 6: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The + upper end of the common-mode voltage range is V -1.5V at 25C, but either or both inputs can go to 36V without damage, + independent of the magnitude of V . Note 7: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be obtained, see typical performance characteristics section. Note 8: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than -0.3V (or 0.3V below the magnitude of the negative power supply, if used). + + Note 9: At output switch point, VO ~ 1.4V, RS=0 with V from 5V to 30V; and over the full input common-mode range (0V to V -1.5V), at 25C. Note 10: Refer to RETS193AX for AP393 military specifications.
Typical Circuit (VCC =5.0VDC)
V+
+5.0VDC
+VIN
+ AP393
3.0K VO
+ AP393 -
100K
+VREF
-
1/4 MM54CXX
Basic Comparator
Driving CMOS
V+
+5VDC
100K 75 pF
4.3K V+ 0 1:100kHz VO
+ AP393 -
10K
1/2 AP393
1/4 DM54XX
V+ 100K
+
100K 100K
Driving TTL
Squarewave Oscillator
Anachip Corp. www.anachip.com.tw 4/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Typical Circuit (Continued) (VCC =5.0VDC)
V+ R1 1M D1 1N914 * 15K
200K 100K 2.0K V+ 0 VO V+
R2 D2 100K 1N914 80 pF
1/2 AP393
6s VO
60s t2 tO t1
-V+ 0
0.1F
1/2 AP393 +
+15VDC
1M
+
1M 1M *For large ratios of R1/R2, D1 can be omitted
200K CRYSTAL f=100KHz
Pulse Generator
V+ 100K 10 +VC FREQUENCY CONTROL VOLTAGE INPUT 50K 0.1F
Crystal Controlled Oscillator
V+
100K 3.0K 5.1K 0.01F
-
500pF
1/2 AP393 +
+ 1/2 AP393 -
3.0K OUTPUT1
V+/2 20K 20K
OUTPUT2
1/2 AP393 +
V+/2
Two-Decade High Frequency VCO
V*=+30VDC +250mVDC < VC < +50VDC 700Hz < fO < 100KHz
V+
V+
+VIN
+ 1/2 AP393
3.0K VO
+VREF
1/2 AP393
3K VO
+VREF
-
+VIN
10K
+
10M
Basic Comparator
Non-Inverting Comparator with Hysteresis
Anachip Corp. www.anachip.com.tw 5/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Typical Circuit (Continued) (VCC =5.0VDC)
V+
V+
+VIN
1/2 AP393
3K VO
-
6.2K VO * STROBE INPUT
1/2 AP393
+
V+
1M
+
1M 1M
* OR LOGIC GATE WITHOUT PULL-UP RESISTOR
Inverting Comparator with Hysteresis
V+
Output Strobing
V+
39K +0.375V 1K 100K 100K 100K 1K
3K
200K +0.075V 1K 100K 100K 100K 1K "0" "1"
3K
1/2 AP393 +
f
1/2 AP393 +
f
A B C
A B C V+ 0
V+ 0 "0" "1"
AND Gate
V+ 2RS
Or Gate
V+ (12VDC) R4 3K VOUT RS +VIN +VREF HI
100K 10K 100K V+ 0 "0" "1" D1 A B C D D2 D3 D4
+ 1/2 AP393 -
1/2 AP393 +
10K LAMP 12 ESB
+ 1/2 AP393
+VREF LOW 2RS 2N2222
ALL DIODES 1N914
-
Large Fan-in AND Gate
Limit Comparator
Anachip Corp. www.anachip.com.tw 6/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Typical Circuit (Continued) (VCC =5.0VDC)
V+
+
100K 100K 2N2222 5.1K
3.0K VO
1/2 AP393 -
+VIN1 -VIN2
1/2 AP393
+
+ 1/2 AP393 -
Comparing Input Voltages of Opposite Polarity
V+ 100K VIN 5.1K 5.1K 1N914 100K
ORing the Outputs
V+ +
5.1K
0
1/2 AP393 +
20M VO
t0
100pF 1N914
1M
10K
1M
1/2 AP393 +
0.001F 1M 1N914
VO 1ms PW t0 t1 V+ 0
10K
Zero Crossing Detector (Single Power Supply)
V+
One-Shot Multivibrator
51K V+ 0 V+ 0 R 100K S 100K 100K
15K S +15V 0
+ 1/2 AP393 -
R VO
Bi-Stable Multivibrator
Anachip Corp. www.anachip.com.tw 7/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Typical Circuit (Continued) (VCC =5.0VDC)
V+
+VIN +4V 1s 0
100K
1M 100K
1M
1/2 AP393 +
10M
560K
15K 40s t0 VO t1 V+ 0
100pF
1/2 AP393 +
10M 240K
62K
One-Shot Multivibrator with Input Lock Out
V+
10K
15K
200K 10K
10M
3.0K
+ 1/2 AP393 10M 3.0K V+ VO3 V+ 0 t0 t3
V3
V 0 t0 t4 +VIN INPUT GATING SIGNAL
+
51K VC1 C1 V2 10K
10K
1/2 AP393 +
+ 1/2 AP393 10M 3.0K V+ V+ VO2 V+ 0 t0 t2
0.001F
51K V+ V3 VC1 V2 V1 0 t0 t1 t2 t3 t4 t 10K
+ 1/2 AP393
VO1
0
t0 t1
V1 51K
-
Time Delay Generator
Anachip Corp. www.anachip.com.tw 8/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Split-Supply Applications (V+=+15VDC and V- =-15 VDC)
V+
51K
51K
10K
2K
3.9K
1/2 AP393 +
2.4K
2.4K
+ 1/2 AP393 8.2K 2K
A
1/2 AP393
B
+
5.1K
1/2 AP393 -
50pF
6.8K
V-
MOS Clock Driver
V+
V+
+ VIN
+ 1/2 AP393 V-
5.1K VO
+ VIN -5 VDC
+ 1/2 AP393 V
5.1K VO
Zero Crossing Detector
Comparator With a Negative Reference
Anachip Corp. www.anachip.com.tw 9/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Typical Characteristics
Supply Current
Input Current
Output Saturation Voltage
Response Time for Various Input Overdrives--Negative Transition
Response Time for Various Input Overdrives--Positive Transition
Anachip Corp. www.anachip.com.tw 10/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Application Information
The AP393 is high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator change states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10k reduces the feedback signal levels and finally, adding even a small amount (1.0 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All input pins of any unused comparators should be tied to the negative supply. The bias network of the AP393 establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 2.0 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device (Note 8). Protection should be provided to prevent the input voltages from going negative more than -0.3 VDC (at 25C). An input clamp diode can be used as shown in the applications section. The output of the AP393 is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the AP393 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the of this device. When the maximum current limit is reached (approximately 16mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60 rSAT of the output transistor. The low offset voltage of the output transistor (1.0 mV) allows the output to clamp essentially to ground level for small load currents.
Marking Information
(Top View)
8 5
Logo Part No. AP393 YY WW X
1 4
ID code: internal Xth week: 01~52 Year: "01" =2001 "02" =2002
~
SOP-8L/PDIP-8L
Anachip Corp. www.anachip.com.tw 11/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Package Information
(1) PDIP-8L (Plastic Dual-in-line Package )
D
E-PIN O0.118 inch
E1
E 15 (4X) PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
7 (4X) eB A2 A
C
L
B S e B1 B2
Symbol A A1 A2 B B1 B2 C D E E1 e L eB S
Dimensions in millimeters Min. Nom. Max. 5.33 0.38 3.1 3.30 3.5 0.36 0.46 0.56 1.4 1.52 1.65 0.81 0.99 1.14 0.20 0.25 0.36 9.02 9.27 9.53 7.62 7.94 8.26 6.15 6.35 6.55 2.54 2.92 3.3 3.81 8.38 8.89 9.40 0.71 0.84 0.97
A1
Dimensions in inches Min. Nom. Max. 0.210 0.015 0.122 0.130 0.138 0.014 0.018 0.022 0.055 0.060 0.065 0.032 0.039 0.045 0.008 0.010 0.014 0.355 0.365 0.375 0.300 0.313 0.325 0.242 0.250 0.258 0.100 0.115 0.130 0.150 0.330 0.350 0.370 0.028 0.033 0.038
Anachip Corp. www.anachip.com.tw 12/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators Package Information (Continued)
(2) SOP- 8L(JEDEC Small Outline Package)
E
H
L VIEW "A" D 7 (4X) A2 A 0.015x45
7 (4X)
A1
e
B y
C
VIEW "A"
Symbol A A1 A2 B C D E e H L y
Dimensions In Millimeters Min. Nom. Max. 1.40 1.60 1.75 0.10 0.25 1.30 1.45 1.50 0.33 0.41 0.51 0.19 0.20 0.25 4.80 5.05 5.30 3.70 3.90 4.10 1.27 5.79 5.99 6.20 0.38 0.71 1.27 0.10 0O 8O
Dimensions In Inches Min. Nom. Max. 0.055 0.063 0.069 0.040 0.100 0.051 0.057 0.059 0.013 0.016 0.020 0.0075 0.008 0.010 0.189 0.199 0.209 0.146 0.154 0.161 0.050 0.228 0.236 0.244 0.015 0.028 0.050 0.004 0O 8O
Anachip Corp. www.anachip.com.tw 13/13
Rev. 1.0 Sep 7, 2004

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